The race to build artificial intelligence has become a contest between nations as much as between companies. Right now, the scarcest resources in that contest are energy and silicon.
And, while America’s NVIDIA currently supplies most of the world’s AI compute, South Korea is building a meaningful AI supply chain of its own.
The country already produces most of the world’s high-bandwidth memory through Samsung and SK Hynix, and it is now working to convert that lead into a foothold in AI compute itself. In that effort, Rebellions is undeniable.
Jake Hertz (left) with Rebellions’ CEO and Co-Founder Sunghyun Park (right) in NYC. All About Circuits image.
Founded in 2020 and transcended to Korea’s first AI-chip unicorn, the company has drawn backing from Samsung, SK Hynix, and Arm, alongside a national growth fund that casts the investment as part of a “K-Nvidia” ambition. With a unique bet on memory-centric design for inference, the company believes that a processor fabricated and funded in Korea can win on cost per token rather than peak compute.
All About Circuits recently sat down in New York City with Rebellions co-founder and CEO Sunghyun Park to learn about the company’s memory-centric approach firsthand.
Rebellions’ Rebel100
Serving a large language model is less a question of arithmetic throughput than of keeping expensive compute fed with data. Every generated token forces the processor to stream model weights and a growing key-value cache out of memory, so bandwidth and capacity, not FLOPS alone, set the floor on how cheaply a chip can produce output.
Rebellions designed the Rebel100 around that constraint. The part is a system-in-package that connects four homogeneous chiplets, each roughly 320 mm², via a UCIe interconnect. Across the package, Rebellions pairs 144 GB of HBM3E running at 4.8 TB/s with 512 MB of on-chip SRAM per die, and rates the device at about 2 PFLOPS of FP8 compute. At ISSCC 2026, the company described the part as the industry’s first quad-chiplet AI accelerator to use UCIe, and claimed H200-class performance within a lower power envelope.
The Rebel100 connects four chiplets over a UCIe interconnect in a single package. (Click on image to enlarge).
For Park, the packaging choice follows directly from how transformer inference behaves. “We are focused on a memory-centric architecture, backed by SK Hynix and Samsung Foundry,” said Park. “Memory and logic are combined into a single accelerator, because transformers require a lot of memory bandwidth.”
”We are designing a 3D-stacked IC where the memory sits right next to the logic, and we co-optimize the two together to enable the most efficient inference.”
Why LLM Inference Rewards Memory Bandwidth
The economics of transformer inference are influenced by a long-running imbalance in chip design. Over the past two decades, arithmetic performance has grown far faster than the bandwidth available to move data on and off the processor, a discrepancy often called the memory wall.
For autoregressive language models the wall is significant, because generating each new token requires reading the full set of model weights along with a key-value cache that expands with every token already produced.
Two design philosophies have emerged in response. One approach keeps the entire working set in on-chip SRAM spread across very large dies, trading capacity for the highest possible bandwidth and the lowest latency at small batch sizes. This is the approach notable players like Cerebras and Groq have taken.
The other approach surrounds the compute with high-bandwidth memory, accepting slightly higher access latency in exchange for the tens of gigabytes of capacity needed to hold large models and long context windows without constant off-package traffic. This is Rebellion’s approach.
Rebellions CEO Sunghyun Park explaining the company’s memory-centric approach. All About Circuits image.
Because SRAM delivers speed but little density, while HBM delivers density at competitive bandwidth, the choice between them sets the markets a given accelerator can serve. Designs optimized for raw tokens per second suit latency-sensitive premium workloads, while capacity-rich designs target high-volume serving, where cost per token rather than peak speed governs the buying decision.
An Open Software Stack and the CUDA Question
Hardware capacity means little without a software path that developers will actually adopt, and that path has historically run through Nvidia’s CUDA. Rebellions is taking the opposite route with its RBLN SDK, building on open components including vLLM, PyTorch, Triton, and Hugging Face rather than a proprietary stack.
Park frames the decision through a historical analogy. “Intel beat IBM not because its silicon was better, but because it embraced Linux while IBM stayed on Unix,” he said. “The same thing is happening now in inference. PyTorch 2.0 and torch.compile give us an abstraction layer over the hardware, so our customers don’t need to care what silicon is underneath. We sacrifice maybe 5 to 10 percent of performance for that, and we think it is worth it.”
The RBLN compiler
That openness raises an obvious question, which Park acknowledges as a central one for the company. If any vendor’s hardware can slot in beneath the same open layers, what stops Rebellions chips from becoming interchangeable commodities?
His answer is that the company intends to compete on cost and energy efficiency rather than on lock-in. “Inference is being commoditized, and the end user does not care which chip generated the token,” he said. “They care how many dollars it takes to generate a thousand tokens, which in a data center comes down to capex and opex. Our moat is efficiency, and not by 20 or 30 percent. We are aiming for two to three times better, because we built the silicon from scratch only for inference.” Those figures are Rebellions’ own targets rather than independently measured results.
Designing for a Moving Target
Committing silicon to a workload that changes monthly is the hardest part of building an inference ASIC, a tension sometimes described as the hardware lottery, in which the models that win are the ones that happen to fit the available hardware. A fixed-function accelerator tuned to one algorithm earns efficiency at the cost of flexibility, while a fully reconfigurable design preserves flexibility but gives much of that efficiency back.
Park describes Rebellions’ position as a deliberate point between those extremes. “We bet about 75 percent on transformers, because we believe they will be the mainstream for at least the next four or five years,” he said. “But we keep design margin for the rest, because the market can change in ways we cannot predict.”
Because of this, the company leans on its chiplet construction and a two-year design pipeline to stay current. Where larger competitors plan on roughly three-year cycles, Park says an execution-focused team can turn a design faster when the market moves. The same modularity also lets Rebellions add a CPU die inside the package to absorb the host and orchestration work that now runs alongside neural inference, including the key-value cache management that long input and output sequences demand.
Park calls the result a “future-proof architecture”, one designed so that an unexpected change in workloads can be answered by swapping a die rather than redesigning the whole part.
Check out this deep dive on Rebellions that All About Circuits published earlier this year.
From Chiplet to Rack
Rebellions has recently started packaging the Rebel100 into full systems. The company has introduced RebelRack, an air-cooled enclosure that houses 32 accelerators within a roughly 5-7 kW envelope, and RebelPod, which scales from 64 to 1,024 accelerators for larger deployments. The build-out is funded by a $400 million pre-IPO round closed in March 2026 at a valuation near $2.34 billion, following a $250 million Series C led by Arm. The company has signaled that a public listing could come sooner rather than later.
Park sees those systems as steps toward a larger goal. “Maybe ten years from now, we are an infrastructure company for AI,” he said. “Our customers will not need to care whether the rack has our chips or someone else’s. They will care about the power budget, the cost budget, and the token throughput of the system we deliver.”
All images used courtesy of Rebellions, except where otherwise noted.
