AMD will add Universal Chiplet Interconnect Express (UCIe) connectivity to its Versal adaptive SoC portfolio for the first time. Select Versal RF Series devices will ship with native support for UCIe 1.1 interfaces, allowing specialized chiplets to be co-packaged with the SoC and to communicate over a low-power, high-bandwidth in-package link.
With UCIe connectivity, the MD Versal RF Series chiplets offer a heterogeneous compute architecture with up to 80 TOPS of DSP compute, integrated RF converters, and SWAP-C benefits.
Production chiplets are expected to be available with select Versal RF Series devices in the fourth quarter of 2027.
From Board-Level Links to In-Package Interconnect
UCIe is an open standard for die-to-die interconnect inside a package. AMD was among its founding members, alongside Intel, TSMC, Samsung, and Arm, when the consortium formed in March 2022. The specification defines a physical layer, a protocol stack, and a compliance program so that chiplets from different vendors can interoperate within a single package. Version 1.1, the revision implemented by the new Versal devices, was published in August 2023 and added reliability mechanisms and broader usage models, including automotive use.
AMD has built its processors from chiplets for years, but those designs rely on proprietary die-to-die links. Adopting an open standard is a different proposition and allows customers to pair AMD silicon with commercial or custom chiplets, rather than redesigning a large monolithic SoC or commissioning a new one for every application. According to AMD, the approach can reduce latency, power, size, development costs, and complexity while allowing designers to reuse proven silicon IP.
The change is most visible at the board level. Integrating RF front ends, AI accelerators, optical interfaces, memory subsystems, or custom ASICs with a Versal device has historically required separate packaged components connected over board-level links—in AMD's case, the GTM2 serialized interfaces. The company says its UCIe implementation offers lower latency and better power efficiency, measured in picojoules per bit at the die-to-die interface, than those external connections.
Select Versal RF Series devices will support up to four independent UCIe-SP (standard-package) interfaces and up to two UCIe-AP (advanced-package) interfaces, providing multi-terabit-per-second aggregate bandwidth inside the package. The two flavors correspond to the standard's two packaging classes: UCIe-SP links chiplets across a conventional organic substrate, while UCIe-AP relies on advanced packaging such as silicon interposers or bridge dies for denser, higher-bandwidth connections. Offering both gives designers a cost-performance choice within the same device family.
Inside the Versal RF Series
The Versal RF Series, introduced in December 2024, integrates high-resolution RF data converters, dedicated hard IP for DSP, AI engines, and programmable logic on a single chip. The devices deliver up to 80 TOPS of heterogeneous DSP compute, and AMD says they combine the functionality of six discrete devices into one package. Launch materials specified up to sixteen 14-bit RF-ADCs sampling at up to 32 GSPS and sixteen 14-bit RF-DACs at up to 16 GSPS.
AMD Versal RF Series UCIe chiplet enablement.
Those capabilities target applications where size, weight, power, and cost are at a premium, such as phased-array radar, electromagnetic spectrum operations, signals intelligence, and satellite communications terminals on the aerospace and defense side, as well as multi-channel test and measurement instruments and wireless research platforms.
A Chiplet Ecosystem for RF Systems
With UCIe in place, AMD envisions co-packaged chiplets spanning third-party RF analog front ends and data converters, AI acceleration, CPUs, GPU-based specialized compute, custom security engines, communications processors, and application-specific ASICs. A radar or communications system that once required several board-mounted devices around the SoC could consolidate them into a single package, reducing interconnect power and freeing up board area.
Production chiplets are expected in the fourth quarter of 2027, which aligns with the Versal RF family's volume ramp. AMD said additional adaptive SoCs will gain UCIe support as the chiplet market matures.
The consortium behind the standard has grown to more than 100 member companies, and the specification has continued to evolve, reaching version 3.0 in August 2025 with data rates up to 64 GT/s. For AMD's adaptive computing portfolio, the Versal RF Series is the entry point into that ecosystem.
